A 24.5–53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS

Author

Dajiang Zhou ; Gang He ; Wei Fei ; Zhixiang Chen ; Jinjia Zhou ; Goto, Satoshi

Author_Institution

Grad. Sch. of Inf., Waseda Univ., Kitakyushu, Japan

fYear

2013

fDate

22-25 Jan. 2013

Firstpage

73

Lastpage

74

Abstract

An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680×4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p 30fps encoding dissipates only 2mW at 0.8V and 9MHz.

Keywords

CMOS integrated circuits; arithmetic codes; binary codes; microprocessor chips; video coding; CABAC architecture; CMOS; H.264/AVC intraframe video encoder chip; energy 24.5 pJ to 53.6 pJ; energy consumption; frequency 9 MHz; hardware efficiency; intraprediction design; power 2 mW; size 65 nm; voltage 0.8 V; Educational institutions; Encoding; Engines; Hardware; Random access memory; Table lookup; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific

Conference_Location

Yokohama

ISSN

2153-6961

Print_ISBN

978-1-4673-3029-9

Type

conf

DOI

10.1109/ASPDAC.2013.6509562

Filename

6509562