Title :
A low power multimedia processor implementing dynamic voltage and frequency scaling technique
Author :
Enomoto, Tetsuya ; Kobayashi, Nao
Author_Institution :
Chuo Univ., Tokyo, Japan
Abstract :
A DVFS controlled 90-nm CMOS multimedia processor was developed. To make full use of the advantages of DVFS, we developed the A2BC algorithm that can predict the optimum clock frequency and the optimum supply voltage. The measured power dissipation of the DVFS controlled multimedia processor was significantly reduced. Thus, DVFS employing the A2BC algorithm is one of the most useful power reduction for future video encoding applications.
Keywords :
CMOS integrated circuits; low-power electronics; microprocessor chips; multimedia systems; A2BC algorithm; CMOS multimedia processor; DVFS; dynamic voltage technique; frequency scaling technique; low power multimedia processor; optimum clock frequency; optimum supply voltage; power dissipation; power reduction; size 90 nm; video encoding applications; Clocks; Encoding; Multimedia communication; Prediction algorithms; Process control; Signal processing algorithms; Streaming media;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4673-3029-9
DOI :
10.1109/ASPDAC.2013.6509563
