Title :
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique
Author :
Yoshimoto, Shusuke ; Terada, M. ; Okumura, Susumu ; Suzuki, Takumi ; Miyano, S. ; Kawaguchi, Hitoshi ; Yoshimoto, Masahiko
Author_Institution :
Grad. Sch. of Syst. Inf., Kobe Univ., Kobe, Japan
Abstract :
This paper presents a novel disturb mitigation technique which achieves low-power and low-voltage SRAM. Our proposed technique consists of a floating bitline technique and a low-swing bitline driver (LSBD). We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The proposed technique achieves 1.52-pJ/access active energy in a write cycle and 72.8-μW leakage power, which are 59.4% and 26.0% better than the conventional write-back technique.
Keywords :
SRAM chips; SRAM test chip; floating bitline technique; leakage power; low power SRAM; low power disturb mitigation technique; low swing bitline driver; low voltage SRAM; power 72.8 muW; size 40 nm; voltage 0.5 V; write back technique; write cycle; CMOS integrated circuits; Educational institutions; Equalizers; MOS devices; Random access memory; Transistors; Very large scale integration;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4673-3029-9
DOI :
10.1109/ASPDAC.2013.6509564
