Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme

Author

Tanakamaru, Shuhei ; Yanagihara, Y. ; Takeuchi, Ken

Author_Institution

Univ. of Tokyo, Tokyo, Japan

fYear

2013

fDate

22-25 Jan. 2013

Firstpage

83

Lastpage

84

Abstract

11-times extended lifetime, 76% reduced error SSD is proposed. The error-prediction LDPC realizes both 7-times faster read and high reliability. Errors are most efficiently corrected by calibrating memory data based on the V_TH, inter-cell coupling, write/erase cycles and data-retention time. The error-recovery scheme with a program-disturb error-recovery pulse and a data-retention error-recovery pulse is also proposed to reduce the program-disturb error and the data-retention error by 76% and 56%, respectively.

Keywords

NAND circuits; error correction codes; flash memories; parity check codes; reliability; EP-LDPC; SSD; data-retention error-recovery pulse; error prediction LDPC; intercell coupling; low density parity check codes; memory data calibration; program-disturb error-recovery pulse; solid-state drives; write-erase cycles; Bit error rate; Computer architecture; Couplings; Decoding; Flash memories; Parity check codes; Reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific

Conference_Location

Yokohama

ISSN

2153-6961

Print_ISBN

978-1-4673-3029-9

Type

conf

DOI

10.1109/ASPDAC.2013.6509567

Filename

6509567