Trends in ECL array technology

Author

Blood, Bill ; Chakravarty, Dev

Author_Institution

Motorola Inc., Chandler, AZ, USA

fYear

1989

fDate

25-28 Sep 1989

Lastpage

37987

Abstract

Trends for future ECL (emitter-coupled logic) gate-array circuits and the technology developments needed to support new products are described. Trends are determined by analyzing product life cycles together with active process development and circuit design research projects. Subjects covered include projected logic densities, array architectures, performance levels, power handling, and memory requirements. Developments are underway in all these areas to keep ECL the technology of choice for high-performance system design

Keywords

application specific integrated circuits; bipolar integrated circuits; emitter-coupled logic; logic arrays; technological forecasting; ECL ASICs; ECL array technology; ECL gate arrays; active process development; array architectures; circuit design research projects; emitter-coupled logic; high-performance system design; logic densities; memory requirements; performance levels; power handling; product life cycles; technology developments; trends; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Design automation; Libraries; Logic arrays; Logic design; Macrocell networks; Packaging;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1989.123173

Filename

123173