DocumentCode :
2072718
Title :
Board on chip-ball grid array (BOC-BGATM) package. A new design for high frequency application (package design and reliability)
Author :
Yew, Chee-Kiang ; Ong, Pang-Hup ; Swee, Yong-Khim ; Min-Yu Chan ; Low, Siu-Waf ; Toh, Jeffrey ; Chan, Jeffrey ; Leong, Chew-Weng
Author_Institution :
Dept. of Memory Packaging Dev., Texas Instrum. Singapore, Singapore
fYear :
1997
fDate :
18-21 May 1997
Firstpage :
353
Lastpage :
357
Abstract :
This Board on chip-Ball grid array (BOC-BGATM) packaging concept has been developed for memory devices to cater for high frequency application. The shorter electric path between IC chip and board enable better electrical performance. This BOC concept is apply to 1.6 Meg DRAM memory chip, with future applications in higher pin counts 64 Meg & 256 Meg DRAM chips and other memory products. This paper unveils the BOC-BGATM packaging concept, it uses a board (substrate) material that is mounted above the silicon chip as in the case of Lead On Chip (LOG) technology. Beside using in DRAM packaging, the concept is applicable to any silicon chips such as VRAM, LOGIC, SRAM, EPROM and other integrated circuit chip which required array form of interconnect. The sawing, mounting, and bonding processes can be carried out on the existing assembly and test equipment. The interconnect from the bond pads to the solder balls is achieved through copper traces and via holes within the substrate. New processes such as underfill, liquid compound encapsulation, ball mounting and reflow need to be implemented. This paper outlines the design and reliability considerations for 16 Meg BOC-BGA package. The design-in computer simulation is carried out at the beginning of packaging design, software are used to access and select the optimum design from Thermal, Electrical and Thermal Stress requirements. This final design will encompass good heat dissipation, low electrical inductance, low stress and warpage characteristics. In package reliability test, the 16 Meg BOC-BGA package pass level 2 & 3 Popcorn Test, Pressure Cooker Test and completed 200 and 500 Temperature Cycling without any external package crack and delamination. Board level solder joint reliability is currently on-going
Keywords :
DRAM chips; integrated circuit packaging; integrated circuit reliability; 16 Mbit; BOC-BGA package design; DRAM memory; IC chip; board on chip-ball grid array; bond pad; computer simulation; copper trace; electrical inductance; heat dissipation; high frequency application; interconnect; liquid compound encapsulation; reflow; reliability; sawing; solder ball mounting; thermal stress; underfill; via hole; warpage; Frequency; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit technology; Lead; Logic arrays; Packaging machines; Silicon; Testing; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 1997. Proceedings., 47th
Conference_Location :
San Jose, CA
ISSN :
0569-5503
Print_ISBN :
0-7803-3857-X
Type :
conf
DOI :
10.1109/ECTC.1997.606192
Filename :
606192
Link To Document :
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