DocumentCode :
2072740
Title :
Low cost chip-scale package
Author :
Teo, Y.C. ; Lim, T.B. ; Ho, H.M. ; Cui, C.Q. ; Tsui, Christina ; Lian, S.C. ; Tan, T.T.
Author_Institution :
Inst. of Microelectron., Singapore
fYear :
1997
fDate :
18-21 May 1997
Firstpage :
358
Lastpage :
362
Abstract :
A chip-scale package has been developed comprising an area-array bond pad die, solder bumped and mounted on a metallic frame. The die is fully encapsulated by an epoxy molding compound. Openings in the encapsulation are created corresponding to the bumps on the die. This allows interconnection from the die to the printed circuit board (PCB) through solder balls. Conventional mold compound, die attach and alloy 42 materials were used. The packaging process takes advantage of existing packaging techniques. This eliminates the costly development of new technology and equipment. Prototypes have been built and subjected to reliability tests. The package is very robust and had passed the JEDEC moisture sensitivity Level 1 test and 1000 cycles of liquid-to-liquid thermal shock test, according to Military Standard 833, Condition C (-65°C to 150°C)
Keywords :
integrated circuit packaging; area-array bond pad die; chip-scale package; die attach; encapsulation; epoxy molding compound; interconnection; liquid-to-liquid thermal shock cycling; metallic frame; moisture sensitivity; mounting; printed circuit board; reliability; solder ball; solder bumping; Bonding; Chip scale packaging; Costs; Encapsulation; Integrated circuit interconnections; Microassembly; Packaging machines; Printed circuits; Prototypes; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 1997. Proceedings., 47th
Conference_Location :
San Jose, CA
ISSN :
0569-5503
Print_ISBN :
0-7803-3857-X
Type :
conf
DOI :
10.1109/ECTC.1997.606193
Filename :
606193
Link To Document :
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