Title :
A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS
Author :
Xin Zhang ; Po-Hung Chen ; Ryu, Yoshikatsu ; Ishida, K. ; Okuma, Yasuyuki ; Watanabe, K. ; Sakurai, Takayasu ; Takamiya, Makoto
Author_Institution :
Univ. of Tokyo, Tokyo, Japan
Abstract :
A low voltage buck DC-DC converter (0.45-V input, 0.4-V output) with on-chip gate boosted (OGB) and clock frequency scaled digital PWM controller is designed in 40-nm CMOS process. The highest efficiency to date is achieved at the output power less than 40μW. In order to compensate for the die-to-die delay variations of a delay line in the proposed digital PWM controller, a linear delay trimming by a logarithmic stress voltage (LSV) scheme with good controllability is also proposed and verified in measurement.
Keywords :
CMOS integrated circuits; DC-DC power convertors; PWM power convertors; CMOS process; clock frequency scaled digital PWM controller; delay line; die to die delay variations; linear delay trimming; logarithmic stress voltage; low voltage buck DC-DC converter; on-chip gate boost technique; Clocks; DC-DC power converters; Delay lines; Delays; Logic gates; Pulse width modulation; Stress;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4673-3029-9
DOI :
10.1109/ASPDAC.2013.6509580
