Title :
Graph-coloring and treescan register allocation using repairing
Author :
Colombet, Quentin ; Boissinot, Benoit ; Brisk, Philip ; Hack, Sebastian ; Rastello, Fabrice
Author_Institution :
LIP, INRIA, Lyon, France
Abstract :
Graph coloring and linear scan are two appealing techniques for register allocation as the underlying formalism are extremely clean and simple. This paper advocates a decoupled approach that first lowers the register pressure by spilling variables, and then performs live ranges splitting/coalescing /coloring in a separate phase; this enables the design of simpler, cleaner, and more efficient register allocators. This paper gives a new and more general approach to deal with register constraints. This approach called repairing does not require pre live range splitting and does not introduce additional spill code. It ignores register constraints during coloring/coalescing, and repairs violated constraints afterwards. We applied this method to both graph based and scan based allocators into a decoupled approach. Here, the Iterated Register Coalescer (IRC) and a scan algorithm that uses Static Single Assignment (SSA) properties, the trees can. Moreover, this paper provides a survey on existing and new techniques of bias coloring during scan approaches. Our experimental evaluation shows for the graph based approach, that we reduced the number of vertices (edges) in the interference graph by 26% (33%) without compromising the quality of the generated code. The treescan algorithm improved the compile time of the allocation process by 6.97× over IRC while providing comparable results for the quality of the generated code.
Keywords :
graph colouring; optimising compilers; bias coloring technique; graph coloring; interference graph; iterated register coalescer; linear scan; range coalescing; range coloring; range splitting; repairing approach; scan algorithm; static single assignment property; treescan algorithm; treescan register allocation; Algorithm design and analysis; Color; Interference; Maintenance engineering; Registers; Resource management; Round robin; Coalescing; Coloring; Fast register allocation; Register constraints; SSA form;
Conference_Titel :
Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2011 Proceedings of the 14th International Conference on
Conference_Location :
Taipei
Print_ISBN :
978-1-4503-0713-0