Title :
A 1856 I/O cell CMOS SOG with half-ns clock skew and a 6 ns RAM
Author :
Ohtani, Toshihiko ; Yoshida, Kenji ; Matsuda, Yukihiko ; Daitoh, Toshihiro ; Mizumura, Hisashi
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A 177 K CMOS sea-gates has been developed by applying a 0.8-μm triple-metal-layer process technology. Its speed reaches 200 ps, and 120 K usable gates can be provided. A high-speed RAM (6 ns typical access time) of high-density type (64 kbit maximum) can be implemented on it. It has 1856 I/O cells which offer much flexibility in the construction of I/O buffers
Keywords :
CMOS integrated circuits; application specific integrated circuits; logic arrays; random-access storage; 0.5 ns; 0.8 micron; 200 ps; 6 ns; 64 kbit; ASIC; CMOS SOG; CMOS sea-gates; I/O buffers; access time; flexibility; gate arrays; high-speed RAM; speed; triple-metal-layer; CMOS process; CMOS technology; Clocks; Large scale integration; Logic circuits; National electric code; Protection; Random access memory; Read-write memory; Routing;
Conference_Titel :
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1989.123175
