Chip-Package co-design of 10 GHz bandwidth low noise active front-end interface

We present in this paper the design of a 10 GHz bandwidth low noise active front end interface. This interface uses a common gate amplifier architecture co-designed with the carrier to die bonding wire transition. The carrier to die transition is used to build a low loss third order low pass filter which is used as input matching cell for the common gate amplifier. This Chip-Package interface allows low fabrication cost because it uses standard bonding wires and low silicon area. The proposed Chip-Package interface is used to design a 3.1-10.6 GHz UWB LNA in a 0.13 mum CMOS technology. The simulated results show a return loss greater than 10 dB with a noise figure lower than 4.5 dB in the 3.1-10.6 GHz UWB FCC frequency range with a power consumption of 8.6 mW and a silicon area of 0.2 mm2.