Title :
Enabling Parametric Feasibility Analysis in real-time calculus driven performance evaluation
Author :
Simalatsar, Alena ; Ramadian, Yusi ; Passerone, Roberto ; Lampka, Kai ; Perathoner, Simon ; Thiele, Lothar
Author_Institution :
EPFL, Lausanne, Switzerland
Abstract :
This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarchical approach that couples the independent and different by nature frameworks of Modular Performance Analysis with Real-time Calculus (MPARTC) and Parametric Feasibility Analysis (PFA). Recent work on Real-time Calculus (RTC) has established an embedding of state-based component models into RTC-driven performance analysis for dealing with more expressive component models. However, with the obtained analysis infrastructure it is possible to analyze components only for a fixed set of parameters, e. g., fixed CPU speeds, fixed buffer sizes etc., such that a big space of parameters remains unstudied. In this paper, we overcome this limitation by integrating the method of parametric feasibility analysis in an RTC-based modeling environment. Using the PFA tool-flow, we are able to find regions for component parameters that maintain feasibility and worst-case properties. As a result, the proposed analysis infrastructure produces a broader range of valid design candidates, and allows the designer to reason about the system robustness.
Keywords :
formal specification; object-oriented programming; process algebra; program diagnostics; reasoning about programs; software metrics; software performance evaluation; CPU speed; PFA tool-flow; RTC-based modeling environment; analysis infrastructure; buffer size; component analysis; compositional; interface metrics; modular performance analysis with real-time calculus; parametric feasibility analysis; real-time calculus driven performance evaluation; real-time constraint; state-based component models; system robustness; Automata; Clocks; Gold; Synchronization; Feasibility areas; System-level Design; Tool integration; Worst-case Analysis;
Conference_Titel :
Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2011 Proceedings of the 14th International Conference on
Conference_Location :
Taipei
Print_ISBN :
978-1-4503-0713-0