A 23.5 GHz Double Stage Low Noise Amplifier Using .13μm CMOS Process with an Innovative Inter-Stage Matching Technique

Author

Rashid, S. M Shahriar ; Roy, Apratim ; Ali, Sheikh Nijam ; Rashid, A.B.M.H.

Author_Institution

Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh

fYear

2009

fDate

24-26 Sept. 2009

Firstpage

1

Lastpage

4

Abstract

This paper demonstrates a 23.5 GHz double stage low noise amplifier using an innovative inter-stage matching technique. The same matching technique is also used at the output of the amplifier for the purpose of output matching. The circuit is designed in IBM .13 mum CMOS process and is simulated using cadence spectre. The simulated responses exhibit a forward gain of 20 dB at 23.5 GHz with a bandwidth of 2.5 GHz. Reverse isolation is less than -47.1 dB. Input and output matching parameters are -23 dB and -28.34 dB respectively. The amplifier achieves a NF of only 4.945 dB at the center frequency and consumes 21.7 mW of power when driven from a 1.2 V power supply. To the best of the authors´ knowledge, double stage low noise amplifier of such high gain and low noise is rarely reported.

Keywords

CMOS integrated circuits; isolation technology; low noise amplifiers; microwave amplifiers; CMOS process; cadence spectre; double stage low noise amplifier; frequency 23.5 GHz; innovative interstage matching technique; power 21.7 mW; reverse isolation; size 0.13 mum; voltage 1.2 V; Bandwidth; CMOS process; Circuit noise; Circuit simulation; Frequency; Gain; Impedance matching; Low-noise amplifiers; Noise measurement; Power amplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications, Networking and Mobile Computing, 2009. WiCom '09. 5th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-3692-7

Electronic_ISBN

978-1-4244-3693-4

Type

conf

DOI

10.1109/WICOM.2009.5301057

Filename

5301057