Return loss optimization of the microprocessor package vertical interconnect

A geometry based parametric model of a differential high-speed line traversing a ten-layer microprocessor package is developed. This model is used to undertake a detailed study of the effect of the various geometrical parameters on the return loss performance of such a package. The forward problem is solved using a fast, full-wave electromagnetic (EM) solver. The effect of various types of routing in the intermediate layers is examined closely. A sensitivity analysis based on parametric sweeps is carried out to identify the key variables. A hierarchical response surface based optimization is carried out to arrive at an optimum structure. A global optimizer based on simulated annealing is harnessed to find the optimum of non-linear and, in general, non-convex functions. The optimized structure exhibits excellent return loss characteristics translating into higher channel bandwidth.