3D via belt technology

Three-dimensional die stacking with vertical interconnections through Si dies is potentially the best semiconductor system integration technique. With its incredibly promising improvements in speed and power dissipation in IC´s, it has attracted increased attention in recent times. But this approach needs to perform through silicon vias at wafer level step and such wafers are not always available. This paper presents a 3D solution for interconnection of a base wafer with standard dies. Firstly, it consists in manufacturing copper pillars dedicated to vertical connection and manufactured around flip-chip position by electroplating. Then dies are connected to the substrate face-down by mu-insert technology. In order to obtain a new surface, the wafer is embedded in a polymer and planarized by grinding enabling copper pillars to be connected. A new rerouting and interconnection system enables a second die hybridization. This report presents the first manufacturing approaches and electrical results.