Board level energy correlation and interconnect reliability modeling under drop impact

Portable products as well as some larger products may see failures by a high strain rate mechanical loading like that seen in a high or low level drop/shock event. Within the portable product industry there is a wide range of product design, usage and loading conditions. Because of this, standards such as JEDEC, which is meant to generate comparative results addressing component reliability, do little or nothing to generalize the reliability of specific assemblies. To do this we need to consider both failure rates and failure mechanisms to better understand how specific loading conditions affect the failure of an assembly. A standard JEDEC style test board was assembled with BGA components and then drop tested with an input of various energy levels. Pad cratering was the failure mode for all assemblies. This allowed for an independent investigation into this one failure mode. During the drop test the energy from the impact event is transferred into the board, which causes a response. A comparison between the response energy and the input energy was made and, for this particular test assembly, the input correlated to the response reasonably well. Upon further investigation it was found that the failure rates correlated well to the energy levels at which it was tested. This allowed for the development of a predictive model based on these empirical results. With the failure mode of all assemblies being pad cratering on the PCB side of the solder joint it allowed for an investigation into the response of individual pads. The fatigue resistance and strength of the PCB pads was measured using pad-level testing techniques. By measuring the fatigue resistance as a function of a fixed load, it was possible to develop an S-N curve for this particular test vehicle. From this it was found that the pad lifetime is also highly dependent on the input level, as was seen in the drop testing of this test vehicle. This study also proposes a method to compare the input energy and the r- esponse energy of the board computed using the finite element method. Good correlation between the measured response energy and the simulated response energy has been achieved. A lifetime predictive model has been developed using the simulated response energy. Furthermore, 3D FEA model has been established using ANSYS implicit solver with consideration of detailed copper pad, trace and solder joint design to describe the dynamic behavior of PCB assembly and to predict the location of failure and failure mode after impact. For correlation studies, the maximum volume average Von Mises stress of PCB-pad interface at critical solder joint location is calculated and correlated well with the N63 impact lives measured during the drop test. This was used to develop an impact life prediction model. Nanoindentation technique is used to measure the material properties of copper trace. In addition to solder joint dimensions and material properties, many other factors, including trace dimensions, component size and PCB thickness were also simulated to investigate their effects on drop impact life of packages.