Selective induction heating for wafer level bonding and packaging

Selective induction heating for wafer level bonding is presented. The purpose of this paper is to investigate the relationships between the geometry of solder loop and temperature distribution in induction heating. Using finite element method (FEM) and IR thermal imager, temperature distribution and variation are explored, which shows that the temperature on the solder loops is a function of the area and edge width in the induction heating. The temperature difference between the solder loop and its center on PCB is about 180deg, which shows an obvious selective heating effect. Thermal images of circle and square solder array indicate uniform temperature distribution on the PCB in the induction heating. Good agreement between measured and simulated temperature variation have been achieved.