DocumentCode :
2074044
Title :
Novel hardware architecture for fast address lookups
Author :
Mehrotra, Pronita ; Franzon, Paul D.
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
fYear :
2002
fDate :
2002
Firstpage :
105
Lastpage :
110
Abstract :
The most time critical part in packet forwarding is the route lookup which determines the next hop address of the packet. The problem of searching for routes in large databases is compounded by the fact that routing tables store variable length prefixes and their corresponding next hop addresses. In order to forward a packet, routers need to find the longest matching prefix for the destination address. The work presented describes a new fast and efficient algorithm for searching a large database. The scheme described requires several accesses to a small, fast on-chip SRAM and only one access to a slower DRAM in order to determine the next hop address. The paper discusses some of the related work and approaches in performing route lookups. It describes the proposed algorithm where only a single off-chip DRAM access is required to determine the next hop address. It discusses some of the details of the hardware implementation and lists some of the results of the scheme. Some of the design issues are also discussed.
Keywords :
DRAM chips; SRAM chips; packet switching; table lookup; telecommunication network routing; DRAM; destination address; efficient algorithm; fast address lookup; fast algorithm; fast on-chip SRAM; hardware architecture; large databases; longest matching prefix; packet forwarding; route lookup; routing tables; variable length prefixes; Burst switching; Cams; Databases; Delay effects; Engines; Hardware; Random access memory; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Switching and Routing, 2002. Merging Optical and IP Technologies. Workshop on
Print_ISBN :
4-88552-184-X
Type :
conf
DOI :
10.1109/HPSR.2002.1024217
Filename :
1024217
Link To Document :
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