Novel through-silicon via technique for 2d/3d SiP and interposer in low-resistance applications

With the demands of miniaturized solutions that are able to handle increased heat dissipation, the use of silicon substrates with through-silicon vias (TSV) in electronics modules becomes more and more interesting. Shorter signal path, better cooling of tracks, better impedance control and smaller foot-prints are some of the advantages. This also avoids some RC delays of long, in-plane interconnects and permits higher clock rate and lower power dissipation. This paper covers one via technology (XiVIAtrade) developed for 2d and 3d System-in-a-package (SiP) for the space and interposer industry. With 300 mum thick Si wafers, 180times180 mum vias have been manufactured with high yield and tested for the low-resistance interconnections region. Resistance measurements show values below 10 mOmega, and no degradation has been observed in performance after harsh environmental tests. The novelty in the technique lies in a constriction inside the via (see Figure 1), resulting in an increased yield during the metal deposition, decreasing plating time for sealing the via and also adding mechanical robustness to the configuration; pull strength is tested to > 20 MPa and shear strength to > 30 MPa. The process sequence is based on today´s available equipment and does not include thinning of wafers. It starts with via-formation by a combination of KOH and DRIE etching from both sides. Together with the first re-distribution layers, the via copper seed layer is sputtered onto both sides followed by standard lithography and copper electroplating. The via is then either open or closed, depending on the process or the design. The paper will discuss details in processing, reliability and application.