Accurate two-step measurement-based parasitic capacitance extraction for high speed memory interface

Accurate estimation of parasitic capacitance at a high speed IO pad is important for memory driver and memory bus designs. A measurement based method is, in general, more accurate than analytical estimates and simulation. A common method is the JEDEC procedure using a vector network analyzer [1]. This paper proposes an improved method, based on a two step measurement process to extract accurate parasitic capacitance. The method has been demonstrated at different process variation points. Moreover, the paper discusses the error in effective capacitance due to on-die bypass capacitance and power bus resistance.