Investigating worst case power noise for LP-DDR2 multi ports impedance network

Low Power DDR2 (LP-DDR2) circuit blocks and buffers are grouped into different partitions, Byte Lanes. The on die power grids interconnects between every Byte Lane is either enlarged or isolated totally from other blocks to reduce the leakage current and maximize the power saving. We observed that the Byte Lane isolation can introduce additional standing wave SSO power noise. The observation differs from mainstream DDR implementation where the SSO noise behaves as a periodic resonance waveform. In order to fully understand the unusual observation, we built a R, L, G, C model to generate the Power Delivery Network (PDN) Impedance Matrix. Then we proposed In Phase SSO (IP-SSO) noise from the PDN impedance matrix as the worst case scenario. With the proposed algorithm, we studied the sensitivity of on die power metal grid and board decoupling capacitors. The result concluded that on die power isolation can further worsen the SSO noise regardless the number of decoupling capacitor on the board. We suggested that on die power grid must be included into the pre-silicon simulation to capture the standing wave and worst case behavior.