An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation

Application of IDDQ testing to LSIs fabricated using advanced process technology is becoming increasingly difficult due to large variability of scaled devices. In this paper, we propose a novel technique that adaptively determines per-chip current-threshold for IDDQ testing to enhance test accuracy. In the proposed technique, process condition of a chip and fault-sensitization vector are first estimated based on measured IDDQ currents through Bayesian inference. Then, using the estimated process condition, a statistical distribution of the leakage current for each test pattern is calculated and suitable current-threshold is determined by the distribution. Simulation experiments demonstrate that the proposed technique can successfully detect a very small leakage fault, down to 16% of the nominal IDDQ current with the test escape ratio of 3.1 %.