Title :
Reducing translation lookaside buffer active power
Author :
Clark, Lawrence T. ; Choi, Byungwoo ; Wilkerson, Michael
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described. Powermill simulations of implementation in a microprocessor on 0.18 μm process technology demonstrate 42% power savings. Circuit implementations, as well as. architectural simulations demonstrating applicability to typical instruction mixes are shown.
Keywords :
buffer storage; circuit simulation; content-addressable storage; embedded systems; integrated circuit measurement; low-power electronics; memory architecture; microprocessor chips; 0.18 micron; Powermill simulations; active power dissipation; architectural simulations; associative structures; associative translation lookaside buffers; battery powered embedded microprocessors; circuit implementations; content addressable memory; dynamic register files; instruction mixes; microprocessor process technology implementation; power reduction techniques; power savings; translation lookaside buffer active power reduction; CADCAM; Circuit simulation; Computer aided manufacturing; Discrete cosine transforms; Energy management; Memory management; Microprocessors; Permission; Radio frequency; Registers;
Conference_Titel :
Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
1-58113-682-X
DOI :
10.1109/LPE.2003.1231825
