BIMOS transistor in thin silicon film and new solutions for ESD protection in FDSOI UTBB CMOS technology

Author

Galy, Ph ; Athanasiou, S. ; Cristoloveanu, S.

Author_Institution

STMicroelectron., Crolles, France

fYear

2015

fDate

26-28 Jan. 2015

Firstpage

29

Lastpage

32

Abstract

The purpose of this study is to evaluate the ESD protection behavior using BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. Using as a reference our measurements in hybrid bulk structures we extend the BIMOS design towards the ultrathin silicon film. Evaluations are done based on 3D TCAD simulation with standard physical models using ACS method and quasi-static DC stress (AVS method).

Keywords

BIMOS integrated circuits; MOSFET; electrostatic discharge; semiconductor device models; silicon-on-insulator; 3D TCAD simulation; ACS method; BIMOS transistor; ESD protection; FDSOI UTBB CMOS technology; high-k metal gate technology; hybrid bulk structures; quasistatic DC stress; size 28 nm; ultrathin silicon film; BiCMOS integrated circuits; Electrostatic discharges; Films; Logic gates; Silicon; Stress; Transistors; BIMOS transistor; CMOS; ESD protection; FDSOI;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on

Conference_Location

Bologna

Type

conf

DOI

10.1109/ULIS.2015.7063765

Filename

7063765