Title :
Fabrication and analysis of vertical p-type InAs-Si nanowire Tunnel FETs
Author :
Cutaia, D. ; Moselund, K.E. ; Borg, M. ; Schmid, H. ; Gignac, L. ; Breslin, C.M. ; Karg, S. ; Uccelli, E. ; Nirmalraj, P. ; Riel, H.
Author_Institution :
IBM Res. - Zurich, Rüschlikon, Switzerland
Abstract :
We report InAs-Si nanowire (NW) Tunnel FETs fabricated inside nanotube templates. High device yield and performances are obtained by optimizing the growth conditions and the fabrication flow using inorganic material as dielectric spacer, atomic-layer-deposition for the metal gate and by scaling the equivalent oxide thickness (EOT). We extract the exponential parameter B of Kane´s tunneling model for direct bandgap (Eg) materials and compare it with experimental results. Moreover, studying the activation energy (EA) for TFETs with different EOTs allows us to distinguish the different conduction mechanisms.
Keywords :
III-V semiconductors; atomic layer deposition; energy gap; field effect transistors; indium compounds; nanotube devices; nanowires; optimisation; silicon; tunnel transistors; EOT; InAs-Si; Kane´s tunneling model; NW; TFET; activation energy; atomic layer deposition; conduction mechanisms; dielectric spacer; direct bandgap materials; equivalent oxide thickness; exponential parameter B extraction; fabrication flow optimization analysis; growth condition optimization; high device yield performances; inorganic material; metal gate; nanotube templates; vertical p-type nanowire tunnel FET; Fabrication; Logic gates; Molecular beam epitaxial growth; Photonic band gap; Silicon; Tunneling; IH-V semiconductor materials; Kane model; hetero-junctions; low-power electronics; nanowires; tunnel transistor;
Conference_Titel :
Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on
Conference_Location :
Bologna
DOI :
10.1109/ULIS.2015.7063773
