Tri-gate In0.53Ga0.47As-on-insulator junctionless field effect transistors

Author

Djara, V. ; Czornomaz, L. ; Daix, N. ; Caimi, D. ; Deshpande, V. ; Uccelli, E. ; Sousa, M. ; Marchiori, C. ; Fompeyrine, J.

Author_Institution

IBM Res. GmbH, Rüschlikon, Switzerland

fYear

2015

fDate

26-28 Jan. 2015

Firstpage

97

Lastpage

100

Abstract

A tri-gate In_0.53Ga_0.47As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture is demonstrated. The devices feature a 20-nm-thick n-In_0.53Ga_0.47As channel doped to 10¹⁸ /cm³ obtained by direct wafer bonding and a 3.5-nm-thick Al₂O₃ gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The impact of the fin width (W_fin) and gate length (L_g) scaling at fixed channel doping (N_d) and equivalent oxide thickness (EOT) on the device performance is discussed and benchmarked.

Keywords

III-V semiconductors; aluminium compounds; atomic layer deposition; field effect transistors; gallium arsenide; indium compounds; wafer bonding; Al₂O₃; EOT; InGaAs; JLFET; PE-ALD; direct wafer bonding; equivalent oxide thickness; fin width scaling; fixed channel doping; gate dielectric deposition; gate length scaling; junctionless field effect transistors; plasma-enhanced atomic layer deposition; size 20 nm; size 3.5 nm; trigate InGaAs-on-insulator; Aluminum oxide; Dielectrics; Indium gallium arsenide; Logic gates; MOSFET; Performance evaluation; Wafer bonding; Direct wafer bonding; Field-effect transistor; High-A dielectrics; InGaAs-OI; Junctionless; Multigate;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on

Conference_Location

Bologna

Type

conf

DOI

10.1109/ULIS.2015.7063782

Filename

7063782