Design methodology for fine-grained leakage control in MTCMOS

Author

Calhoun, Benton H. ; Honore, Frank A. ; Chandrakasan, Anantha

Author_Institution

MIT, Cambridge, MA, USA

fYear

2003

fDate

25-27 Aug. 2003

Firstpage

104

Lastpage

109

Abstract

Multi-threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead. MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enables gate-level insertion of sleep devices for sequential and combinational circuits. A fabricated 0.13 μm, dual V_T test chip employs this methodology to implement a low-power FPGA core with gate-level sleep FETs and over 8× measured standby current reduction. The methodology allows local sleep regions that reduce leakage in active configurable logic blocks (CLBs) by up to 2.2× (measured) for some CLB configurations.

Keywords

CMOS logic circuits; combinational circuits; field programmable gate arrays; integrated circuit design; integrated circuit testing; leakage currents; logic design; logic testing; sequential circuits; 0.13 micron; CLB configurations; MTCMOS designs; active configurable logic block; block level standby leakage; combinational circuits; delay overhead; design methodology; dual threshold voltage test chip; fine-grained leakage control; gate-level sleep FET; gate-level sleep device insertion; low-power FPGA core; multi-threshold CMOS; sequential circuits; sleep devices; sneak leakage paths; standby leakage power; Circuit testing; Combinational circuits; Current measurement; Delay; Design methodology; FETs; Field programmable gate arrays; Logic; Semiconductor device measurement; Sleep;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on

Print_ISBN

1-58113-682-X

Type

conf

DOI

10.1109/LPE.2003.1231844

Filename

1231844