DocumentCode :
2076004
Title :
ILP-based optimization of sequential circuits for low power
Author :
Gao, Feng ; Hayes, John P.
Author_Institution :
Adv. Comput. Archit. Lab, Michigan Univ., Ann Arbor, MI, USA
fYear :
2003
fDate :
25-27 Aug. 2003
Firstpage :
140
Lastpage :
145
Abstract :
The power consumption of a sequential circuit can be reduced by decomposing it into subcircuits which can be turned off when inactive. Power can also be reduced by careful state encoding. Modeling a given circuit as a finite-state machine, we formulate its decomposition into submachines as an integer linear programming (ILP) problem, and automatically generate the ILP model with power minimization as the objective. A simple, but powerful state encoding method is used for the submachines to further reduce power consumption. We present experimental results which show that circuits designed by our approach consume 30% to 90% less power than conventional circuits.
Keywords :
circuit CAD; circuit optimisation; encoding; finite state machines; integrated circuit design; integrated logic circuits; logic CAD; low-power electronics; minimisation; sequential circuits; FSM; ILP-based optimization; finite-state machine; integer linear programming problem; power consumption reduction; sequential circuits; state encoding method; Algorithm design and analysis; Encoding; Energy consumption; Integer linear programming; Logic; Minimization; Permission; Power dissipation; Power generation; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
1-58113-682-X
Type :
conf
DOI :
10.1109/LPE.2003.1231850
Filename :
1231850
Link To Document :
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