• DocumentCode
    2076016
  • Title

    Simultaneous Vt selection and assignment for leakage optimization

  • Author

    Rivastava, An Ku r S

  • Author_Institution
    Dept. of ECE, Maryland Univ., College Park, MD, USA
  • fYear
    2003
  • fDate
    25-27 Aug. 2003
  • Firstpage
    146
  • Lastpage
    151
  • Abstract
    This paper presents a novel approach for leakage optimization through simultaneous Vt selection and assignment. Vt selection implies deciding the right value for Vt and assignment implies deciding which gates should be assigned which threshold value. The proposed algorithm is a general mathematical formulation that can be trivially extended to multiple threshold voltages (more than two). Traditional leakage optimization strategies either assume the prespecification of threshold values or are good only for two thresholds. The presented formulation is based on a linear programming approach under the piecewise linear approximation of delay/leakage vs threshold curves. The algorithm was incorporated in SIS. Experimental results indicate that on some benchmarks having more that two thresholds was beneficial for leakage.
  • Keywords
    circuit CAD; circuit optimisation; delays; integrated circuit design; leakage currents; linear programming; piecewise linear techniques; leakage optimization; linear programming approach; multiple threshold voltages; piecewise linear approximation; simultaneous Vt selection/assignment; Circuits; Delay effects; Dynamic voltage scaling; Educational institutions; Leakage current; Logic design; Logic programming; Optimization methods; Permission; Piecewise linear techniques;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on
  • Print_ISBN
    1-58113-682-X
  • Type

    conf

  • DOI
    10.1109/LPE.2003.1231851
  • Filename
    1231851