DocumentCode
2076045
Title
Effective graph theoretic techniques for the generalized low power binding problem [IC high level synthesis]
Author
Davoodi, Azadeh ; Srivastava, An Kur
Author_Institution
Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
fYear
2003
fDate
25-27 Aug. 2003
Firstpage
152
Lastpage
157
Abstract
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given a fixed number of resources and multiple architectures for the resources. First, the generalized low power binding problem is formulated as an integer linear programming (ILP) problem which happens to be an NP-complete task to solve. Then two polynomial-time heuristics are proposed that provide a speedup of up to 13.7 with an extremely low penalty for power when compared to the optimal ILP solution for our selected benchmarks.
Keywords
circuit optimisation; graph theory; high level synthesis; linear programming; low-power electronics; IC high level synthesis; NP-complete problem; fixed resource number; generalized low power binding problem; graph theoretic heuristics; integer linear programming; multiple resource architectures; polynomial-time heuristics; Algorithm design and analysis; Design optimization; Educational institutions; Energy consumption; Graph theory; High level synthesis; Iterative algorithms; Permission; Polynomials; Power dissipation;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on
Print_ISBN
1-58113-682-X
Type
conf
DOI
10.1109/LPE.2003.1231852
Filename
1231852
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