Title :
A clock delayed sleep mode domino logic for wide dynamic OR gate
Author :
Oh, Kwang-II ; Kim, Lee-Sup
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea
Abstract :
A high performance and low power clock delayed sleep mode (CDSM) domino logic is proposed for wide fan-in domino logic. The CDSM-domino logic not only improves the robustness but also reduces the active and stand-by power. The proposed scheme reduces delay by 21%, dynamic power by 16%, and leakage power by 91% respectively compared to the typical wide fan-in domino logic in 0.18 μm CMOS technology. In addition, the sleep mode entrance power is reduced to 10-5 of the HS-domino logic.
Keywords :
CMOS logic circuits; integrated circuit design; leakage currents; logic design; logic gates; logic simulation; low-power electronics; 0.18 micron; CMOS; HS-domino logic; active power reduction; clock delayed sleep mode domino logic; leakage power reduction; low power CDSM-domino logic; sleep mode entrance power; stand-by power reduction; wide dynamic OR gate; wide fan-in domino logic; CMOS logic circuits; CMOS technology; Clocks; Degradation; Delay; Energy consumption; Logic design; MOS devices; Maintenance; Robustness;
Conference_Titel :
Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
1-58113-682-X
DOI :
10.1109/LPE.2003.1231857
