A novel architecture for nanometer scale low power VLSI design

Power consumption is one of the major threads in CMOS technology. International technology road-map for semiconductors (ITRS) [1] reports that leakage power dissipation may come to dominate total power consumption. Although Leakage power was negligible at 0.18μ technology and above, in nano scale technology, but when the technology is decreases these leakage powers are the top most concern for VLSI circuit designer. As the technology feature size shrink static power consumption dominant the dynamic power exponentially and this static power consumption is known as a sub-threshold leakage. Sub-threshold leakage is a leakage that is arises by creating a weak inversion channel between drain to source. However, tunneling current through gate oxide insulator, channel punch through current and gate current due to hot-carrier injection are also responsible for semiconductor power consumption. Although gate-oxide thickness will be reduced as the technology decreases in nano scale, but this reduction causes sub-threshold leakage. So, there were several method was proposed to tackle the leakage. However, every proposed method has some trade-offs between power, delay and area, in this paper novel common vdd and gnd technique is proposed to overcome the semiconductor leakage and this technique has excellent tradeoffs between power, delay and area, moreover this method will be new weapon for low power VLSI circuit designer.