DocumentCode :
2076508
Title :
Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers
Author :
Pirro, L. ; Ionica, I. ; Mescot, X. ; Cristoloveanu, S. ; Ghibaudo, G. ; Faraone, L.
Author_Institution :
IMEP-LAHC, Grenoble-INP, Grenoble, France
fYear :
2015
fDate :
26-28 Jan. 2015
Firstpage :
249
Lastpage :
252
Abstract :
We investigate for the first time the quasi-static capacitance technique in pseudo-MOSFET configuration for the characterization of bare SOI wafers. We show the difference between the measurements performed with slow and fast ramp speed and compare them with split-CV characteristics. We discuss the impact of experimental parameters such as ramp speed, probe pressure and number of probes. Finally, we present an experimental procedure, based on an original physical model, to extract the interface trap density.
Keywords :
MOSFET; capacitance measurement; interface states; probes; silicon-on-insulator; Dit extraction; bare SOI wafers; experimental procedure; interface trap density; original physical model; probe number; probe pressure; pseudo-MOSFET configuration; quasistatic capacitance measurements; ramp speed; split-CV characteristics; Capacitance; Capacitance measurement; Current measurement; Films; Logic gates; Probes; Silicon; SOI; capacitance measurement; interface trap density; pseudo-MOSFET; quasi-static;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on
Conference_Location :
Bologna
Type :
conf
DOI :
10.1109/ULIS.2015.7063820
Filename :
7063820
Link To Document :
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