• DocumentCode
    2076527
  • Title

    Impact of the diameter of vertical nanowire-tunnel FETs with Si and SiGe source composition on analog parameters

  • Author

    Bordallo, C.C.M. ; Sivieri, V.B. ; Martino, J.A. ; Agopian, P.G.D. ; Rooyackers, R. ; Vandooren, A. ; Simoen, E. ; Thean, A. ; Claeys, C.

  • Author_Institution
    LSI/PSI, Univ. of Sao Paulo, Sao Paulo, Brazil
  • fYear
    2015
  • fDate
    26-28 Jan. 2015
  • Firstpage
    253
  • Lastpage
    256
  • Abstract
    In this work, the impact of the diameter on vertical nanowire Tunnel FETs analog parameters is evaluated experimentally and by numerical simulation, comparing two different source compositions, one with Si and another with Si73Ge27. The SiGe source device presents a higher tunneling current when compared with the Si source device, resulting in an increase of both transconductance (gm) and output conductance (gD). For a diameter (Def) higher than 70nm, the reduction of Def decreases both gm and gD due to the decrease of the conducting area. In order to extrapolate the results for smaller diameters, some numerical simulations were performed and show that the predominant transport mechanism for 30 nm diameter is band-to-band tunneling (BTBT), which are more drain voltage dependent. As a result, a strong degradation of gD and intrinsic voltage gain (Av) was observed due to the increase of the generation rate by the enhanced tunneling.
  • Keywords
    Ge-Si alloys; field effect transistors; nanowires; numerical analysis; tunnel transistors; BTBT; Si73Ge27; SiGe; analog parameters; band-to-band tunneling; generation rate; intrinsic voltage gain; numerical simulation; predominant transport mechanism; size 30 nm; source composition; source device; transconductance; tunneling current; tunneling enhancement; vertical nanowire-tunnel FET; Field effect transistors; Logic gates; Numerical simulation; Performance evaluation; Silicon; Silicon germanium; Tunneling; Analog Parameters; SiGe Source; TFET; Vertical Nanowire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on
  • Conference_Location
    Bologna
  • Type

    conf

  • DOI
    10.1109/ULIS.2015.7063821
  • Filename
    7063821