A simple compact model for carrier distribution and its application in single-, double- and triple-gate junctionless transistors

Author

Fanyu Liu ; Ionica, Irina ; Bawedin, Maryline ; Cristoloveanu, Sorin

Author_Institution

IMEP-LAHC, MINATEC, Grenoble, France

fYear

2015

fDate

26-28 Jan. 2015

Firstpage

277

Lastpage

280

Abstract

We propose a very simple compact model that accurately reproduces the carrier profiles in multiple-gate junctionless transistors. The threshold voltage is easily derived from the carrier distribution. The model takes into account the interaction of the various gates and provides the maximum body size of single- and double-gate transistors enabling full depletion (off-state). TCAD simulations validate the accuracy of our model.

Keywords

MOSFET; semiconductor device models; technology CAD (electronics); TCAD simulations; carrier distribution; double-gate junctionless transistors; simple compact model; single-gate junctionless transistors; threshold voltage; triple-gate junctionless transistors; Charge carrier density; Doping; Logic gates; Mathematical model; Semiconductor process modeling; Threshold voltage; Transistors; carrier densities; coupling effect; full depletion; junctionless transistors; partial depletion; threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on

Conference_Location

Bologna

Type

conf

DOI

10.1109/ULIS.2015.7063827

Filename

7063827