ECL and BiCMOS application specific memories (ASMs) on a single chip

The increasing magnitude of bipolar ASIC (application-specific integrated circuit) arrays allows single-chip designs of up to 50 K gates. To take full advantage of these solitary chip systems, high-performance, ECL, bipolar arrays with large and small on-chip efficient memory architectures must be available. Motorola´s MCA4 50 k ECL customer definable array (CDA), an approach that meets these needs through offering gate array or optional semicustom portions of ECL (emitter coupled logic) bipolar and BiCMOS custom memory on a single chip, is discussed. It is shown that ECL memories with less than 2-ns access times are practical for configurations of up to 4 kb. For larger memories, embedded BiCMOS RAMs of up to 180 kb can be implemented on half of an otherwise 50 k ECL array. Besides process flexibility, the array allows the designer to perform layout techniques using tiles (fully diffused macros adhering to the gate array row grid) as fundamental building blocks for the memory cells and RAM auxiliary logic. Implications of using embedded memories and large arrays are addressed