DocumentCode :
2076781
Title :
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files
Author :
Ahin, K.M.B. ; Patra, Priyadarsan ; Najm, Farid N.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fYear :
2003
fDate :
25-27 Aug. 2003
Firstpage :
294
Lastpage :
297
Abstract :
We introduce an architectural-level power, area, and latency estimator for multi-ported, pipelined register files. Strengths of the proposed approach include the handling of pipelined operation and clock power, the simulation-based device size estimation, and the ability to handle user-specified timing constraints. The model proposed can be used as a standalone estimation and design exploration tool for register files and register-file type structures, or it can be incorporated into a high-level performance simulator to add power estimation capabilities.
Keywords :
file organisation; pipeline processing; power consumption; simulation; ESTIMA; architectural-level power estimator; architectural-level power models; design exploration tool; high-level performance simulator; latency estimator; multiported pipelined register files; simulation based device size estimation; standalone estimation; user-specified timing constraints; Circuit simulation; Clocks; Delay; Energy consumption; Microprocessors; Permission; Radio frequency; Registers; Space exploration; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
1-58113-682-X
Type :
conf
DOI :
10.1109/LPE.2003.1231881
Filename :
1231881
Link To Document :
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