• DocumentCode
    2076819
  • Title

    Voltage scheduling under unpredictabilities: a risk management paradigm [logic design]

  • Author

    Davoodi, Azadeh ; Srivastava, Ankur

  • Author_Institution
    Electr. & Comput. Eng. Dept., Univ. of Maryland, College Park, MD, USA
  • fYear
    2003
  • fDate
    25-27 Aug. 2003
  • Firstpage
    302
  • Lastpage
    305
  • Abstract
    This paper addresses the problem of voltage scheduling in unpredictable situations. The voltage scheduling problem assigns voltages to operations such that the power is minimized under a clock cycle constraint. In the presence of unpredictabilities, meeting the clock constraint cannot be guaranteed. This paper proposes a novel risk management based technique to solve this problem. The risk management paradigm assigns a quantified value to the amount of risk the designer is willing to take on the clock cycle constraint. The algorithm then assigns voltages in order to meet the expected value of clock cycle constraint while keeping the maximum delay within the specified ´risk´ and minimizing the power.
  • Keywords
    circuit optimisation; high level synthesis; integrated circuit design; low-power electronics; risk management; clock cycle constraints; constrained maximum delay; high level synthesis; low power voltage scheduling; power optimization; predictability; risk management technique; unpredictability; Algorithm design and analysis; Clocks; Constraint optimization; Delay; Design automation; Design optimization; Low voltage; Permission; Risk management; Scheduling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on
  • Print_ISBN
    1-58113-682-X
  • Type

    conf

  • DOI
    10.1109/LPE.2003.1231883
  • Filename
    1231883