Experimental demonstration of planar SiGe on Si TFETs with counter doped pocket

Author

Blaeser, S. ; Richter, S. ; Wirths, S. ; Trellenkamp, S. ; Buca, D. ; Zhao, Q.T. ; Manti, S.

Author_Institution

Peter Grunberg Inst. (PGI) Forschungszentrum Julich, Jülich, Germany

fYear

2015

fDate

26-28 Jan. 2015

Firstpage

297

Lastpage

300

Abstract

This paper presents both experimental and TCAD simulation results on a planar tunneling field-effect transistor (TFET) using compressively strained Si_0.45Ge_0.55 on Si. Introducing a counter doped pocket at the source tunnel junction in combination with a selective and self-adjusted silicidation to enlarge the tunneling area enables line tunneling aligned with the gate electric field which results in an enhanced band-to-band tunneling (BTBT) probability, increased on-current I_on and reduced inverse subthreshold swing (SS).

Keywords

Ge-Si alloys; electric fields; field effect transistors; probability; semiconductor device models; silicon; technology CAD (electronics); tunnel transistors; BTBT probability; Si TFET; Si_0.45Ge_0.55-Si; TCAD simulation; band-to-band tunneling probability; counter doped pocket; gate electric field; line tunneling; planar SiGe; planar tunneling field effect transistor; selective silicidation; self-adjusted silicidation; source tunnel junction; Doping; Junctions; Logic gates; Radiation detectors; Silicon; Silicon germanium; Tunneling; SiGe; TFET; counter doped pocket; line tunneling; selective; self-adjusted silicidation;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on

Conference_Location

Bologna

Type

conf

DOI

10.1109/ULIS.2015.7063832

Filename

7063832