Title :
A graphical system for hierarchical specifications and checkups of VLSI circuits
Author :
Becker, B. ; Burch, Th ; Hotz, G. ; Kiel, D. ; Kolla, R. ; Molitor, P. ; Osthof, H.G. ; Pitsch, G. ; Sparmann, U.
Author_Institution :
Univ. des Saarlandes, Saarbrucken, Germany
Abstract :
The most important frontend components of the VLSI design system CADIC are presented. The first one allows graphical specification of recursively defined circuits. The other one allows the designer to navigate the synthesized layout following the hierarchical specification to check e.g. CADIC´s hierarchical optimisations or to control the outcome of test generation algorithms
Keywords :
VLSI; circuit layout CAD; engineering graphics; CADIC; VLSI circuits; VLSI design system; graphical specification; graphical system; hierarchical specification; recursively defined circuits; synthesized layout; test generation algorithms; Circuit synthesis; Design optimization; Integrated circuit synthesis; Layout; Logic design; Navigation; Power supplies; Routing; Statistics; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
DOI :
10.1109/EDAC.1990.136640
