Verilog library development using Cadence Central Delay Calculator

The Honeywell Solid State Electronics Center (SSEC) is a semiconductor supplier that offers a variety of products and services such as sensors, memories and ASIC libraries and toolkits. The Honeywell rad-hard RICMOS ASIC libraries have traditionally been based on the Mentor platform, but recently, an effort was undertaken to develop a Verilog capability for customers who wanted to use Verilog. This paper outlines the Verilog design methodology developed by Honeywell, and how the Verilog library development effort used new tools such as the new Cadence Central Delay Calculator to implement the timing simulation and back-annotation capabilities