A purely behavioral data structure for accurate high level timing simulation of synchronous designs

It is difficult to develop pure behavioral Verilog models of synchronous digital systems (such as a CISC microprocessor) that produce accurate timing information using only the built-in reg declaration and blocking assignment statements. The authors present a novel behavioral module definition that can be instantiated instead of a reg to abstractly model synchronous register transfers with blocking assignment statements. The technique is easy to use because of Verilog´s hierarchical naming and because the module automatically deals with the clock. Although simple register transfers could be modeled with non-blocking assignment, this technique has the advantage that it can be extended easily to deal with arbitrary depth pipelines. To introduce the technique, the authors examine the modeling of several instructions from the Motorola 68HC11 in both a multicycle implementation that matches the Motorola documentation and in a faster pipelined implementation