An automated design methodology for FPGA-based Multi-Gbps LDPC decoders

Low density parity check (LDPC) codes are error-correcting codes that offer huge advantages in terms of coding gain, throughput and power dissipation. Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However hardware implementation of LDPC decoders using traditional hardware description language (HDL) based approach is a complex and time consuming task. This paper presents an efficient automated high level approach to designing LDPC decoders using a collection of high level modelling tools. High data rate Multi-Gbps LDPC decoders have been developed and implemented on FPGA using the proposed methodology. These Multi-Gbps LDPC decoders can be utilized in the latest generation of high data rate wireless communication such as WLAN, WiMAX and DVB-S2.