Title :
DYNORA: a new caching technique
Author :
Srivatsan, P. ; Sudarshan, P.B. ; Bhaskaran, P.P.
Author_Institution :
Dept. of Electr. & Electron. Eng., Sri Venkateswara Coll. of Eng., Chennai, India
Abstract :
Cache design for high performance computing requires the realization of two seemingly disjoint goals of higher hit ratios at reduced access times. Recent research advocates the use of "resizable" caches to exploit cache requirement variability in programs. Existing schemes for resizable caches effectively employ either of the two fundamentally different methods: by changing the cache organization itself or by using a proper resizing strategy, that is, either static or dynamic resizing. Our paper looks at a new dynamic resizing strategy that aims at run time manipulation of the cache parameters to improve its performance. Two algorithms for dynamic reconfiguration are proposed and the results explained.
Keywords :
cache storage; memory architecture; DYNORA; cache design; cache parameter; cache parameters; cache requirement variability; caching technique; dynamic reconfiguration; dynamic resizing strategy; high performance computing; higher hit ratio; hit ratios; reduced access time; resizing strategy; run time manipulation; Circuits; Computer architecture; Design engineering; Educational institutions; Energy efficiency; Hardware; Heuristic algorithms; High performance computing; Interleaved codes; Manipulator dynamics;
Conference_Titel :
Digital System Design, 2003. Proceedings. Euromicro Symposium on
Conference_Location :
Belek-Antalya, Turkey
Print_ISBN :
0-7695-2003-0
DOI :
10.1109/DSD.2003.1231902