Timing modeling of datapath layout for synthesis

This paper presents an HDL synthesis method that maps a Verilog description of an ASIC to a hierarchical netlist. The method partitions the ASIC´s behavior into control logic and datapath. The control logic is synthesized using components from a gate library. The datapath is synthesized using components from a datapath library. For designs with timing constraints, the synthesis method generates accurate timing information of a synthesized bit-sliced datapath in three steps: 1) builds a layout model netlist of the datapath, 2) performs detailed timing verification on this netlist, 3) generates Meta Model which specifies the electrical and timing information of the bit-sliced datapath. This Meta Model is then used by our synthesis tool to optimize the control logic around the datapath. We also use the timing information of the Meta Model to resynthesize a new datapath with improved timing performance