A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2-μm CMOS for 2B1Q high bit-rate digital subscriber line transceivers

Author

Samueli, Henry ; Joshi, Robindra B. ; Wong, Bennett C. ; Daneshrad, Babak ; Tan, Loke Kun ; Kruse, David ; Nicholas, Henry T.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

1991

fDate

12-15 May 1991

Abstract

A 60-MHz 64-tap adaptive FIR filter chip has been fabricated in 1.2-μm CMOS which can implement either an echo canceller or decision-feedback equalizer for 2B1Q high bit-rate digital subscriber line (HDSL) transceivers. The 4.3-mm×4.3-mm, 30000-transistor chip is a complete self-contained adaptive filter which incorporates the LMS algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths which are often required in high-bit-rate transceivers. At a 60-MHz clock rate the echo canceller/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud

Keywords

CMOS integrated circuits; adaptive filters; digital communication systems; echo suppression; equalisers; feedback; subscriber loops; transceivers; 1.2 micron; 2B1Q; 60 MHz; 64 tap configuration; LMS algorithm; adaptive FIR filter chip; coefficient updating; decision-feedback equalizer; digital subscriber line; echo canceller; high-bit-rate transceivers; Adaptive filters; CMOS digital integrated circuits; Copper; DSL; Decision feedback equalizers; Echo cancellers; Finite impulse response filter; Pulse transformers; Signal processing algorithms; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164060

Filename

164060