Title :
Technology mapping using Boolean matching and don´t care sets
Author :
Mailhot, Frédéric ; De Micheli, Giovanni
Author_Institution :
Stanford Univ., CA, USA
Abstract :
The authors describe a new approach to technology mapping where matchings are recognized by means of Boolean operations. The matching algorithm uses tautology checking based on Shannon decompositions. They show how to use the symmetry and unateness properties to speed-up the Boolean matching algorithm. They examine how don´t care information can be used during Boolean matching. The algorithms have been implemented in program Ceres and tested on the 1989 MCNC benchmark circuits
Keywords :
Boolean functions; circuit CAD; logic CAD; Boolean matching; Boolean operations; Ceres; MCNC benchmark circuits; Shannon decompositions; don´t care sets; matching algorithm; symmetry; tautology checking; technology mapping; unateness properties; Algorithm design and analysis; Circuit synthesis; Circuit testing; Integrated circuit interconnections; Libraries; Logic circuits; Logic functions; Logic testing; Partitioning algorithms; Timing;
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
DOI :
10.1109/EDAC.1990.136647
