DocumentCode
2077347
Title
Technology mapping using Boolean matching and don´t care sets
Author
Mailhot, Frédéric ; De Micheli, Giovanni
Author_Institution
Stanford Univ., CA, USA
fYear
1990
fDate
12-15 Mar 1990
Firstpage
212
Lastpage
216
Abstract
The authors describe a new approach to technology mapping where matchings are recognized by means of Boolean operations. The matching algorithm uses tautology checking based on Shannon decompositions. They show how to use the symmetry and unateness properties to speed-up the Boolean matching algorithm. They examine how don´t care information can be used during Boolean matching. The algorithms have been implemented in program Ceres and tested on the 1989 MCNC benchmark circuits
Keywords
Boolean functions; circuit CAD; logic CAD; Boolean matching; Boolean operations; Ceres; MCNC benchmark circuits; Shannon decompositions; don´t care sets; matching algorithm; symmetry; tautology checking; technology mapping; unateness properties; Algorithm design and analysis; Circuit synthesis; Circuit testing; Integrated circuit interconnections; Libraries; Logic circuits; Logic functions; Logic testing; Partitioning algorithms; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location
Glasgow
Print_ISBN
0-8186-2024-2
Type
conf
DOI
10.1109/EDAC.1990.136647
Filename
136647
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