Title :
The one million gate ASIC challenge: not with behavioral modeling and synthesis
Author_Institution :
Pragmatic C Software Corp., San Francisco, CA, USA
Abstract :
The large ASIC IC design problem is discussed within the Verilog hardware description language research program. Large ASIC design using the behavioral design with synthesis method is shown to be infeasible by showing that evolutionary improvement of traditional gate level tools and increased logic designer skill is both necessary and sufficient. Suggestions for applying Verilog to large gate level ASIC design and for improving Verilog in the accurate timing gate level simulation area are made
Keywords :
application specific integrated circuits; circuit analysis computing; specification languages; Verilog hardware description language; behavioral design; gate level tools; one million gate ASIC challenge; timing gate level simulation; Application specific integrated circuits; CMOS technology; Circuit synthesis; Computer aided manufacturing; Design methodology; Hardware design languages; Integrated circuit modeling; Integrated circuit synthesis; Logic design; Timing;
Conference_Titel :
Verilog HDL Conference, 1994., International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-5655-7
DOI :
10.1109/IVC.1994.323745
