The one million gate ASIC challenge: not with behavioral modeling and synthesis

The large ASIC IC design problem is discussed within the Verilog hardware description language research program. Large ASIC design using the behavioral design with synthesis method is shown to be infeasible by showing that evolutionary improvement of traditional gate level tools and increased logic designer skill is both necessary and sufficient. Suggestions for applying Verilog to large gate level ASIC design and for improving Verilog in the accurate timing gate level simulation area are made