Gate sizing in MOS digital circuits with linear programming

Author

Berkelaar, Michel R C M ; Jess, Jochen A G

Author_Institution

Fac. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands

fYear

1990

fDate

12-15 Mar 1990

Firstpage

217

Lastpage

221

Abstract

A solution is presented to tune the delay of a circuit composed of cells to a prescribed value, while minimizing power consumption. The tuning is performed by adapting the load drive capabilities of the cells. This optimization problem is mapped onto a linear program, which is then solved by the simplex algorithm. This approach guarantees to find the global optimum, and has proven feasible for circuits of up to several thousand cells. The method can be used with any convex delay model. Results show that circuits can be speeded up by a factor of 2 at a cost of only 10 to 30% of extra power

Keywords

MOS integrated circuits; circuit CAD; combinatorial circuits; linear programming; logic CAD; logic gates; MOS digital circuits; cell circuit delay tuning; convex delay model; gate sizing; global optimum; linear program; linear programming; load drive; optimization problem; power consumption; simplex algorithm; Capacitance; Circuit optimization; Delay; Design automation; Digital circuits; Energy consumption; Linear programming; Newton method; Optimization methods; Tuned circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990., EDAC. Proceedings of the European

Conference_Location

Glasgow

Print_ISBN

0-8186-2024-2

Type

conf

DOI

10.1109/EDAC.1990.136648

Filename

136648