DocumentCode
2077373
Title
Generating ASIC test vectors with Verilog
Author
Cummings, Clifford E.
Author_Institution
Tektronix Inc., Beaverton, OR, USA
fYear
1994
fDate
14-16 Mar 1994
Firstpage
63
Lastpage
70
Abstract
Compiling a design verification test suite is a non-trivial task. Creating that test suite to satisfy an ASIC vendor can be even more difficult. An awareness of existing Verilog HDL capabilities may assist design engineers in the creation of ASIC test vectors to satisfy ASIC-vendor vector requirements. This paper outlines simple Verilog techniques which demonstrate Verilog´s power not only for describing hardware, but for creating ASIC test vectors
Keywords
application specific integrated circuits; integrated circuit testing; logic CAD; specification languages; ASIC test vectors; HDL capabilities; Verilog; design verification test; Application specific integrated circuits; Automatic testing; Binary search trees; Design engineering; Hardware design languages; Monitoring; Power engineering and energy; Power generation; Test pattern generators; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Verilog HDL Conference, 1994., International
Conference_Location
Santa Clara, CA
Print_ISBN
0-8186-5655-7
Type
conf
DOI
10.1109/IVC.1994.323746
Filename
323746
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